359 lines
7.2 KiB
Plaintext
359 lines
7.2 KiB
Plaintext
/*
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* ARM Ltd. Fast Models
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*
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* Versatile Express (VE) system model
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* ARMCortexA15x4CT
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* ARMCortexA7x4CT
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* RTSM_VE_Cortex_A15x4_A7x4.lisa
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*/
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/dts-v1/;
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/memreserve/ 0xff000000 0x01000000;
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/ {
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model = "RTSM_VE_CortexA15x4-A7x4";
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arm,vexpress,site = <0xf>;
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compatible = "arm,rtsm_ve,cortex_a15x4_a7x4", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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clusters {
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#address-cells = <1>;
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#size-cells = <0>;
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cluster0: cluster@0 {
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reg = <0>;
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// freqs = <500000000 600000000 700000000 800000000 900000000 1000000000 1100000000 1200000000>;
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cores {
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#address-cells = <1>;
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#size-cells = <0>;
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core0: core@0 {
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reg = <0>;
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};
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core1: core@1 {
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reg = <1>;
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};
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core2: core@2 {
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reg = <2>;
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};
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core3: core@3 {
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reg = <3>;
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};
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};
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};
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cluster1: cluster@1 {
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reg = <1>;
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// freqs = <350000000 400000000 500000000 600000000 700000000 800000000 900000000 1000000000>;
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cores {
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#address-cells = <1>;
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#size-cells = <0>;
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core4: core@0 {
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reg = <0>;
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};
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core5: core@1 {
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reg = <1>;
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};
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core6: core@2 {
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reg = <2>;
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};
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core7: core@3 {
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reg = <3>;
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};
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};
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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cluster = <&cluster0>;
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core = <&core0>;
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// clock-frequency = <1000000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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cluster = <&cluster0>;
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core = <&core1>;
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// clock-frequency = <1000000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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cluster = <&cluster0>;
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core = <&core2>;
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// clock-frequency = <1000000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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cluster = <&cluster0>;
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core = <&core3>;
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// clock-frequency = <1000000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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cluster = <&cluster1>;
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core = <&core4>;
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// clock-frequency = <800000000>;
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cci-control-port = <&cci_control2>;
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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cluster = <&cluster1>;
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core = <&core5>;
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// clock-frequency = <800000000>;
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cci-control-port = <&cci_control2>;
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};
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cpu6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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cluster = <&cluster1>;
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core = <&core6>;
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// clock-frequency = <800000000>;
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cci-control-port = <&cci_control2>;
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};
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cpu7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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cluster = <&cluster1>;
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core = <&core7>;
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// clock-frequency = <800000000>;
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cci-control-port = <&cci_control2>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x80000000>;
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};
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cci@2c090000 {
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compatible = "arm,cci-400", "arm,cci";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x2c090000 0 0x1000>;
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ranges = <0x0 0x0 0x2c090000 0x10000>;
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control2: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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dcscb@60000000 {
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compatible = "arm,rtsm,dcscb";
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reg = <0 0x60000000 0 0x1000>;
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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gic-cpuif@0 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <0>;
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cpu = <&cpu0>;
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};
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gic-cpuif@1 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <1>;
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cpu = <&cpu1>;
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};
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gic-cpuif@2 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <2>;
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cpu = <&cpu2>;
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};
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gic-cpuif@3 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <3>;
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cpu = <&cpu3>;
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};
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gic-cpuif@4 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <4>;
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cpu = <&cpu4>;
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};
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gic-cpuif@5 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <5>;
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cpu = <&cpu5>;
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};
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gic-cpuif@6 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <6>;
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cpu = <&cpu6>;
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};
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gic-cpuif@7 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <7>;
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cpu = <&cpu7>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc@0 {
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/* ACLK clock to the AXI master port on the test chip */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <30000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "extsaxiclk";
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};
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oscclk1: osc@1 {
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/* Reference clock for the CLCD */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <10000000 80000000>;
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#clock-cells = <0>;
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clock-output-names = "clcdclk";
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};
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smbclk: oscclk2: osc@2 {
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/* Reference clock for the test chip internal PLLs */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <33000000 100000000>;
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#clock-cells = <0>;
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clock-output-names = "tcrefclk";
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};
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 6 &gic 0 6 4>,
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<0 0 7 &gic 0 7 4>,
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<0 0 8 &gic 0 8 4>,
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<0 0 9 &gic 0 9 4>,
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<0 0 10 &gic 0 10 4>,
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<0 0 11 &gic 0 11 4>,
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<0 0 12 &gic 0 12 4>,
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<0 0 13 &gic 0 13 4>,
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<0 0 14 &gic 0 14 4>,
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<0 0 15 &gic 0 15 4>,
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<0 0 16 &gic 0 16 4>,
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<0 0 17 &gic 0 17 4>,
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<0 0 18 &gic 0 18 4>,
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<0 0 19 &gic 0 19 4>,
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<0 0 20 &gic 0 20 4>,
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<0 0 21 &gic 0 21 4>,
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<0 0 22 &gic 0 22 4>,
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<0 0 23 &gic 0 23 4>,
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<0 0 24 &gic 0 24 4>,
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<0 0 25 &gic 0 25 4>,
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<0 0 26 &gic 0 26 4>,
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<0 0 27 &gic 0 27 4>,
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<0 0 28 &gic 0 28 4>,
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<0 0 29 &gic 0 29 4>,
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<0 0 30 &gic 0 30 4>,
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<0 0 31 &gic 0 31 4>,
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<0 0 32 &gic 0 32 4>,
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<0 0 33 &gic 0 33 4>,
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<0 0 34 &gic 0 34 4>,
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<0 0 35 &gic 0 35 4>,
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<0 0 36 &gic 0 36 4>,
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<0 0 37 &gic 0 37 4>,
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<0 0 38 &gic 0 38 4>,
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<0 0 39 &gic 0 39 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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/include/ "rtsm_ve-motherboard.dtsi"
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};
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};
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/include/ "clcd-panels.dtsi"
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