23 lines
911 B
Plaintext
23 lines
911 B
Plaintext
===================================================================
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Power Architecture CPU Binding
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Copyright 2013 Freescale Semiconductor Inc.
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Power Architecture CPUs in Freescale SOCs are represented in device trees as
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per the definition in ePAPR.
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In addition to the ePAPR definitions, the properties defined below may be
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present on CPU nodes.
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PROPERTIES
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- fsl,eref-*
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Usage: optional
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Value type: <empty>
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Definition: The EREF (EREF: A Programmer.s Reference Manual for
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Freescale Power Architecture) defines the architecture for Freescale
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Power CPUs. The EREF defines some architecture categories not defined
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by the Power ISA. For these EREF-specific categories, the existence of
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a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
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name with all uppercase letters converted to lowercase, indicates that
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the category is supported by the implementation.
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