164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
#ifndef SUNXI_MMC_H
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#define SUNXI_MMC_H
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/* speed mode */
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#define DS26_SDR12 (0)
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#define HSSDR52_SDR25 (1)
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#define HSDDR52_DDR50 (2)
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#define HS200_SDR104 (3)
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#define HS400 (4)
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#define MAX_SPD_MD_NUM (5)
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/* frequency point */
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#define CLK_400K (0)
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#define CLK_25M (1)
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#define CLK_50M (2)
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#define CLK_100M (3)
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#define CLK_150M (4)
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#define CLK_200M (5)
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#define MAX_CLK_FREQ_NUM (8)
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/*
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timing mode
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1: output and input are both based on phase
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3: output is based on phase, input is based on delay chain
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4: output is based on phase, input is based on delay chain.
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it also support to use delay chain on data strobe signal.
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*/
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#define SUNXI_MMC_TIMING_MODE_1 1U
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#define SUNXI_MMC_TIMING_MODE_3 3U
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#define SUNXI_MMC_TIMING_MODE_4 4U
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#define MMC_CLK_SAMPLE_POINIT_MODE_1 3U
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#define MMC_CLK_SAMPLE_POINIT_MODE_3 64U
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#define MMC_CLK_SAMPLE_POINIT_MODE_4 64U
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#define TM1_OUT_PH90 (0)
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#define TM1_OUT_PH180 (1)
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#define TM1_IN_PH90 (0)
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#define TM1_IN_PH180 (1)
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#define TM1_IN_PH270 (2)
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#define TM3_OUT_PH90 (0)
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#define TM3_OUT_PH180 (1)
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#define TM4_OUT_PH90 (0)
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#define TM4_OUT_PH180 (1)
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/* smhc0&1 */
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struct sunxi_mmc_timing_mode1 {
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u32 cur_spd_md;
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u32 cur_freq;
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u8 odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u32 sample_point_cnt;
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u8 cur_odly;
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u8 cur_sdly;
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};
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struct sunxi_mmc_timing_mode3 {
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u32 cur_spd_md;
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u32 cur_freq;
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u8 odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u32 sample_point_cnt;
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u32 sdly_unit_ps;
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u8 dly_calibrate_done;
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u8 cur_odly;
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u8 cur_sdly;
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};
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/* smhc2 */
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struct sunxi_mmc_timing_mode4 {
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u32 cur_spd_md;
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u32 cur_freq;
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u8 odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 dsdly[MAX_CLK_FREQ_NUM];
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u8 def_odly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_sdly[MAX_SPD_MD_NUM*MAX_CLK_FREQ_NUM];
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u8 def_dsdly[MAX_CLK_FREQ_NUM];
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u32 sample_point_cnt;
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u32 sdly_unit_ps;
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u32 dsdly_unit_ps;
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u8 dly_calibrate_done;
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u8 cur_odly;
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u8 cur_sdly;
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u8 cur_dsdly;
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};
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struct sunxi_mmc_des {
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u32 :1,
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dic :1, /* disable interrupt on completion */
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last_des :1, /* 1-this data buffer is the last buffer */
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first_des :1, /* 1-data buffer is the first buffer,
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0-data buffer contained in the next descriptor is 1st buffer */
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des_chain :1, /* 1-the 2nd address in the descriptor is the next descriptor address */
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end_of_ring :1, /* 1-last descriptor flag when using dual data buffer in descriptor */
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:24,
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card_err_sum :1, /* transfer error flag */
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own :1; /* des owner:1-idma owns it, 0-host owns it */
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#define SDXC_DES_NUM_SHIFT 12 /* smhc2!! */
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#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
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u32 data_buf1_sz :16,
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data_buf2_sz :16;
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u32 buf_addr_ptr1;
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u32 buf_addr_ptr2;
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};
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struct sunxi_mmc_host {
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u32 mmc_no;
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u32 hclkbase;
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u32 hclkrst;
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u32 mclkbase;
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u32 database;
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u32 fatal_err;
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u32 clock; /* @clock, bankup current clock at host, is updated when configure clock over */
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u32 mod_clk;
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struct sunxi_mmc *reg;
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struct sunxi_mmc *reg_bak;
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struct sunxi_mmc_des* pdes;
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/*sample delay and output deley setting*/
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u32 timing_mode;
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struct sunxi_mmc_timing_mode1 tm1;
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struct sunxi_mmc_timing_mode3 tm3;
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struct sunxi_mmc_timing_mode4 tm4;
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/* @retry_cnt used to count the retry times at a spcific speed mode and frequency during initial process or
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tuning process. it is always equal or less than the number of sample point.
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*/
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u32 retry_cnt;
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struct mmc *mmc;
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struct mmc_config cfg;
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/*sample delay and output deley setting*/
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u32 raw_int_bak;
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u32 sample_mode;
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};
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//#define TUNING_LEN (1)//The address which store the tuninng pattern
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//#define TUNING_ADD (38192-TUNING_LEN)//The address which store the tuninng pattern
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#define TUNING_LEN (10)//The length of the tuninng pattern
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#define TUNING_ADD (38192-2-TUNING_LEN)//The address which store the tuninng pattern
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#define REPEAT_TIMES (30)
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#define SAMPLE_MODE (2)
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//secure storage relate
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#define MAX_SECURE_STORAGE_MAX_ITEM 32
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#define SDMMC_SECURE_STORAGE_START_ADD (6*1024*1024/512)//6M
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#define SDMMC_ITEM_SIZE (4*1024/512)//4K
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#endif /* SUNXI_MMC_H */
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