499 lines
11 KiB
Plaintext
499 lines
11 KiB
Plaintext
/*
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* ARM Ltd. Juno Plaform
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*
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* Fast Models FVP v2 support
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Juno";
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compatible = "arm,juno", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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};
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cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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};
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cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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};
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x0 0x7f000000>,
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<0x00000008 0x80000000 0x1 0x80000000>;
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};
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/* memory@14000000 {
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device_type = "memory";
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reg = <0x00000000 0x14000000 0x0 0x02000000>;
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}; */
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x2c010000 0 0x1000>,
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<0x0 0x2c02f000 0 0x1000>,
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<0x0 0x2c04f000 0 0x2000>,
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<0x0 0x2c06f000 0 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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msi0: msi@2c1c0000 {
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compatible = "arm,gic-msi";
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reg = <0x0 0x2c1c0000 0 0x10000
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0x0 0x2c1d0000 0 0x10000
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0x0 0x2c1e0000 0 0x10000
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0x0 0x2c1f0000 0 0x10000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 0xff01>,
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<GIC_PPI 14 0xff01>,
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<GIC_PPI 11 0xff01>,
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<GIC_PPI 10 0xff01>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 60 4>,
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<GIC_SPI 61 4>,
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<GIC_SPI 62 4>,
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<GIC_SPI 63 4>;
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0xC4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xC4000003>;
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migrate = <0xC4000005>;
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};
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pci0: pci@30000000 {
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compatible = "arm,pcie-xr3";
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device_type = "pci";
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reg = <0 0x7ff30000 0 0x1000
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0 0x7ff20000 0 0x10000
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0 0x40000000 0 0x10000000>;
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bus-range = <0 255>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000
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0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000
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0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 136 4
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0 0 0 2 &gic 0 137 4
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0 0 0 3 &gic 0 138 4
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0 0 0 4 &gic 0 139 4>;
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};
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scpi: scpi@2b1f0000 {
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compatible = "arm,scpi-mhu";
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reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */
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<0x0 0x2e000000 0x0 0x10000>; /* Payload area */
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interrupts = <0 36 4>, /* low priority interrupt */
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<0 35 4>, /* high priority interrupt */
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<0 37 4>; /* secure channel interrupt */
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#clock-cells = <1>;
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clock-output-names = "a57", "a53", "gpu", "hdlcd0", "hdlcd1";
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};
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hdlcd0_osc: scpi_osc@3 {
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compatible = "arm,scpi-osc";
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#clock-cells = <0>;
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clocks = <&scpi 3>;
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frequency-range = <23000000 210000000>;
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clock-output-names = "pxlclk0";
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};
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hdlcd1_osc: scpi_osc@4 {
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compatible = "arm,scpi-osc";
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#clock-cells = <0>;
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clocks = <&scpi 4>;
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frequency-range = <23000000 210000000>;
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clock-output-names = "pxlclk1";
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};
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soc_uartclk: refclk72738khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <7273800>;
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clock-output-names = "juno:uartclk";
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};
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soc_refclk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "juno:clk24mhz";
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};
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mb_eth25mhz: clk25mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "ethclk25mhz";
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};
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soc_usb48mhz: clk48mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "clk48mhz";
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};
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soc_smc50mhz: clk50mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "smc_clk";
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_faxiclk: refclk533mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <533000000>;
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clock-output-names = "faxi_clk";
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};
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soc_fixed_3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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memory-controller@7ffd0000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0 0x7ffd0000 0 0x1000>;
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interrupts = <0 86 4>,
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<0 87 4>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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chip5-memwidth = <16>;
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};
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dma0: dma@0x7ff00000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0x7ff00000 0 0x1000>;
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interrupts = <0 95 4>,
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<0 88 4>,
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<0 89 4>,
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<0 90 4>,
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<0 91 4>,
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<0 108 4>,
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<0 109 4>,
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<0 110 4>,
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<0 111 4>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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clocks = <&soc_faxiclk>;
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clock-names = "apb_pclk";
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};
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soc_uart0: uart@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x1000>;
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interrupts = <0 83 4>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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dmas = <&dma0 1
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&dma0 2>;
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dma-names = "rx", "tx";
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};
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/* this UART is reserved for secure software.
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soc_uart1: uart@7ff70000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff70000 0x0 0x1000>;
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interrupts = <0 84 4>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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}; */
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ulpi_phy: phy@0 {
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compatible = "phy-ulpi-generic";
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reg = <0x0 0x94 0x0 0x4>;
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phy-id = <0>;
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};
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ehci@7ffc0000 {
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compatible = "snps,ehci-h20ahb";
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/* compatible = "arm,h20ahb-ehci"; */
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reg = <0x0 0x7ffc0000 0x0 0x10000>;
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interrupts = <0 117 4>;
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clocks = <&soc_usb48mhz>;
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clock-names = "otg";
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phys = <&ulpi_phy>;
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};
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ohci@0x7ffb0000 {
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compatible = "generic-ohci";
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reg = <0x0 0x7ffb0000 0x0 0x10000>;
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interrupts = <0 116 4>;
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clocks = <&soc_usb48mhz>;
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clock-names = "otg";
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};
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i2c@0x7ffa0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0x0 0x7ffa0000 0x0 0x1000>;
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interrupts = <0 104 4>;
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clock-frequency = <400000>;
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i2c-sda-hold-time-ns = <500>;
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clocks = <&soc_smc50mhz>;
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dvi0: dvi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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};
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dvi1: dvi-transmitter@71 {
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compatible = "nxp,tda998x";
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reg = <0x71>;
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};
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};
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/* mmci@1c050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x0 0x1c050000 0x0 0x1000>;
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interrupts = <0 73 4>,
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<0 74 4>;
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max-frequency = <12000000>;
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vmmc-supply = <&soc_fixed_3v3>;
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clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>;
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clock-names = "mclk", "apb_pclk";
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}; */
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hdlcd@7ff60000 {
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compatible = "arm,hdlcd";
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reg = <0 0x7ff60000 0 0x1000>;
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interrupts = <0 85 4>;
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clocks = <&hdlcd0_osc>;
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clock-names = "pxlclk";
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i2c-slave = <&dvi0>;
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/* display-timings {
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native-mode = <&timing0>;
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timing0: timing@0 {
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/* 1024 x 768 framebufer, standard VGA timings * /
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clock-frequency = <65000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hback-porch = <160>;
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hsync-len = <136>;
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vfront-porch = <3>;
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vback-porch = <29>;
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vsync-len = <6>;
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};
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}; */
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};
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hdlcd@7ff50000 {
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compatible = "arm,hdlcd";
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reg = <0 0x7ff50000 0 0x1000>;
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interrupts = <0 93 4>;
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clocks = <&hdlcd1_osc>;
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clock-names = "pxlclk";
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i2c-slave = <&dvi1>;
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display-timings {
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native-mode = <&timing1>;
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timing1: timing@1 {
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/* 1024 x 768 framebufer, standard VGA timings */
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clock-frequency = <65000>;
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hactive = <1024>;
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vactive = <768>;
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hfront-porch = <24>;
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hback-porch = <160>;
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hsync-len = <136>;
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vfront-porch = <3>;
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vback-porch = <29>;
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vsync-len = <6>;
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};
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};
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 15>;
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interrupt-map = <0 0 0 &gic 0 68 4>,
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<0 0 1 &gic 0 69 4>,
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<0 0 2 &gic 0 70 4>,
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<0 0 3 &gic 0 160 4>,
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<0 0 4 &gic 0 161 4>,
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<0 0 5 &gic 0 162 4>,
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<0 0 6 &gic 0 163 4>,
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<0 0 7 &gic 0 164 4>,
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<0 0 8 &gic 0 165 4>,
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<0 0 9 &gic 0 166 4>,
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<0 0 10 &gic 0 167 4>,
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<0 0 11 &gic 0 168 4>,
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<0 0 12 &gic 0 169 4>;
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motherboard {
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model = "V2M-Juno";
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arm,hbi = <0x252>;
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arm,vexpress,site = <0>;
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arm,v2m-memory-map = "rs1";
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compatible = "arm,vexpress,v2p-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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usb@5,00000000 {
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compatible = "nxp,usb-isp1763";
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reg = <5 0x00000000 0x20000>;
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bus-width = <16>;
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interrupts = <4>;
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};
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ethernet@2,00000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <2 0x00000000 0x10000>;
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interrupts = <3>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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clocks = <&mb_eth25mhz>;
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vdd33a-supply = <&soc_fixed_3v3>; /* change this */
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vddvario-supply = <&soc_fixed_3v3>; /* and this */
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};
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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kmi@060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <8>;
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clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <8>;
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clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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wdt@0f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x10000>;
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interrupts = <7>;
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clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x10000>;
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interrupts = <9>;
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clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
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clock-names = "timclken1", "apb_pclk";
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x10000>;
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interrupts = <9>;
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clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
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clock-names = "timclken1", "apb_pclk";
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x10000>;
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interrupts = <0>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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};
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};
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};
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};
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};
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